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The Top 20 Vhdl Asic Open Source Projects

Open source projects categorized as Vhdl Asic
Categories > Hardware > Asic
Categories > Hardware > Vhdl
Clash Compiler ⭐ 1,336
Haskell to VHDL/Verilog/SystemVerilog compiler
total releases 87most recent commit 3 months ago
Fusesoc ⭐ 1,065
Package manager and build abstraction tool for FPGA/ASIC development
dependent packages 5total releases 26most recent commit 3 months agopypi fusesoc} Downloads
Vunit ⭐ 678
VUnit is a unit testing framework for VHDL/SystemVerilog
dependent packages 5total releases 87most recent commit 23 days agopypi vunit-hdl} Downloads
Poc ⭐ 324
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
most recent commit 4 years ago
Rggen ⭐ 261
Code generation tool for configuration and status registers
total releases 62most recent commit 3 months ago
Surf ⭐ 259
A huge VHDL library for FPGA development
most recent commit 5 months ago
Ztachip ⭐ 172
Opensource software/hardware platform to build edge AI solutions deployed on FPGA or custom ASIC hardware.
most recent commit 3 months ago
Neotrng ⭐ 113
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
most recent commit 6 months ago
Siafpgaminer ⭐ 44
VHDL FPGA design of an optimized Blake2b pipeline to mine Siacoin
most recent commit 6 years ago
Hdlab Fpga Development Board ⭐ 43
Open source FPGA development platform
most recent commit 9 months ago
Awesome Hwd Tools ⭐ 41
A curated list of awesome open source hardware design tools
most recent commit a year ago
Design And Asic Implementation Of 32 Point Fft Processor ⭐ 20
I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of a
most recent commit 5 months ago
Aes Gcm 128 192 256 Bits ⭐ 14
Configurable AES-GCM IP (128, 192, 256 bits)
most recent commit 4 months ago
Ipecc ⭐ 13
A VHDL IP for ECC (Elliptic Curve Cryptography) hardware acceleration
most recent commit 3 months ago
Hdl Modules ⭐ 10
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
most recent commit 3 months ago
Go Hdl ⭐ 9
Thdl is a tool for easing the work with hardware description languages.
most recent commit a year ago
Aes Over Pcie ⭐ 9
A VHDL implementation of 128 bit AES encryption with a PCIe interface.
most recent commit 7 years ago
Mastering Fpgasic Book ⭐ 8
📖 Mastering FPGASIC Book
most recent commit 2 years ago
Verificationip ⭐ 7
Deprecated - This library has been replaced by OsvvmLibraries. The links to the submodules will not be updated to the new versions.
most recent commit 4 years ago
Tinyuart ⭐ 5
Lightweight UART core in VHDL
most recent commit 2 years ago
The 2 Most Depended On Vhdl Asic Open Source Projects
Fusesoc ⭐ 1,065
Package manager and build abstraction tool for FPGA/ASIC development
dependent packages 5total releases 26latest release November 17, 2023most recent commit 3 months agopypi fusesoc} Downloads
Vunit ⭐ 678
VUnit is a unit testing framework for VHDL/SystemVerilog
dependent packages 5total releases 87latest release April 23, 2023most recent commit 23 days agopypi vunit-hdl} Downloads
The 4 Latest Releases In Vhdl Asic Open Source Projects
Fusesoc ⭐ 1,065
Package manager and build abstraction tool for FPGA/ASIC development
dependent packages 5total releases 26latest release November 17, 2023most recent commit 3 months agopypi fusesoc} Downloads
Clash Compiler ⭐ 1,336
Haskell to VHDL/Verilog/SystemVerilog compiler
total releases 87latest release November 11, 2023most recent commit 3 months ago
Rggen ⭐ 261
Code generation tool for configuration and status registers
total releases 62latest release October 18, 2023most recent commit 3 months ago
Vunit ⭐ 678
VUnit is a unit testing framework for VHDL/SystemVerilog
dependent packages 5total releases 87latest release April 23, 2023most recent commit 23 days agopypi vunit-hdl} Downloads
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