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The Top 23 Verilog Asic Open Source Projects

Open source projects categorized as Verilog Asic
Categories > Hardware > Asic
Categories > Hardware > Verilog
Clash Compiler ⭐ 1,336
Haskell to VHDL/Verilog/SystemVerilog compiler
total releases 87most recent commit 3 months ago
Serv ⭐ 1,158
SERV - The SErial RISC-V CPU
most recent commit 4 months ago
Openlane ⭐ 1,148
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
most recent commit a month ago
Fusesoc ⭐ 1,065
Package manager and build abstraction tool for FPGA/ASIC development
dependent packages 5total releases 26most recent commit 3 months agopypi fusesoc} Downloads
Riscv ⭐ 364
RISC-V CPU Core (RV32IM)
most recent commit 3 years ago
Cores ⭐ 302
Various HDL (Verilog) IP Cores
most recent commit 3 years ago
Biriscv ⭐ 300
32-bit Superscalar RISC-V CPU
most recent commit 3 years ago
Rggen ⭐ 261
Code generation tool for configuration and status registers
total releases 62most recent commit 3 months ago
Aes ⭐ 238
Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
most recent commit a year ago
Async_fifo ⭐ 173
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
most recent commit a year ago
Open Register Design Tool ⭐ 169
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
most recent commit 9 months ago
Qflow ⭐ 164
Qflow full end-to-end digital synthesis flow for ASIC designs
most recent commit 3 months ago
Awesome Fpga ⭐ 150
A collection of resources on FPGA devices and development in general
most recent commit 7 years ago
Usb_cdc ⭐ 131
Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
most recent commit 4 months ago
Tekno Kizil ⭐ 129
KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi
most recent commit 9 months ago
Logic ⭐ 121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
most recent commit 4 years ago
Openlane2 ⭐ 99
The next generation of OpenLane, rewritten from scratch with a modular architecture
most recent commit 3 months ago
Kamikaze ⭐ 88
Light-weight RISC-V RV32IMC microcontroller core.
most recent commit 7 years ago
Awesome Dv ⭐ 76
Awesome ASIC design verification
most recent commit 2 years ago
Verilog Parser ⭐ 68
A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
most recent commit 5 years ago
Hdlgen ⭐ 60
HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve
most recent commit 6 months ago
Corsair ⭐ 52
Control and Status Register map generator for HDL projects
total releases 8most recent commit a year ago
Airisc_core_complex ⭐ 48
Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional periperals for embedded AI applications and smart sensors.
most recent commit a year ago
The 2 Most Depended On Verilog Asic Open Source Projects
Fusesoc ⭐ 1,065
Package manager and build abstraction tool for FPGA/ASIC development
dependent packages 5total releases 26latest release November 17, 2023most recent commit 3 months agopypi fusesoc} Downloads
Peakrdl ⭐ 48
Control and status register code generator toolchain
dependent packages 4total releases 11latest release October 26, 2023most recent commit 5 months agopypi peakrdl} Downloads
The 6 Latest Releases In Verilog Asic Open Source Projects
Fusesoc ⭐ 1,065
Package manager and build abstraction tool for FPGA/ASIC development
dependent packages 5total releases 26latest release November 17, 2023most recent commit 3 months agopypi fusesoc} Downloads
Clash Compiler ⭐ 1,336
Haskell to VHDL/Verilog/SystemVerilog compiler
total releases 87latest release November 11, 2023most recent commit 3 months ago
Peakrdl ⭐ 48
Control and status register code generator toolchain
dependent packages 4total releases 11latest release October 26, 2023most recent commit 5 months agopypi peakrdl} Downloads
Rggen ⭐ 261
Code generation tool for configuration and status registers
total releases 62latest release October 18, 2023most recent commit 3 months ago
Libsv ⭐ 6
An open source, parameterized SystemVerilog digital hardware IP library
total releases 3latest release January 31, 2022most recent commit 2 years ago
Corsair ⭐ 52
Control and Status Register map generator for HDL projects
total releases 8latest release September 26, 2021most recent commit a year ago
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