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The Top 10 Verilog Asic Hdl Open Source Projects

Open source projects categorized as Verilog Asic Hdl
Categories > Hardware > Asic
Categories > Hdl
Categories > Hardware > Verilog
Async_fifo ⭐ 173
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
most recent commit a year ago
Logic ⭐ 121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
most recent commit 4 years ago
Hdlgen ⭐ 60
HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve
most recent commit 6 months ago
My Verilog Examples ⭐ 22
A place to keep my synthesizable verilog examples.
most recent commit a year ago
Svlogger ⭐ 11
SystemVerilog Logger
most recent commit a year ago
Mastering Fpgasic Book ⭐ 8
📖 Mastering FPGASIC Book
most recent commit 2 years ago
Wrapped_rgb_mixer ⭐ 7
Demo project for the Zero to ASIC Course.
most recent commit a year ago
Frequency_counter ⭐ 6
Project 2.2 Frequency counter
most recent commit a year ago
Libsv ⭐ 6
An open source, parameterized SystemVerilog digital hardware IP library
total releases 3most recent commit 2 years ago
Gost 28147 89 ⭐ 5
Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher
most recent commit 7 years ago
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