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The Top 19 Asic Hdl Open Source Projects

Open source projects categorized as Asic Hdl
Categories > Hardware > Asic
Categories > Hdl
Surf ⭐ 259
A huge VHDL library for FPGA development
most recent commit 5 months ago
Tensil ⭐ 218
Open source machine learning accelerators
most recent commit 2 years ago
Livehd ⭐ 192
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
total releases 4most recent commit 3 months ago
Async_fifo ⭐ 173
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
most recent commit a year ago
Logic ⭐ 121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
most recent commit 4 years ago
Pygears ⭐ 93
HW Design: A Functional Approach
dependent packages 1total releases 21most recent commit 2 years agopypi pygears} Downloads
Hdlgen ⭐ 60
HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve
most recent commit 6 months ago
Dfiant ⭐ 56
DFiant: A Dataflow Hardware Descripition Language
dependent packages 4total releases 3most recent commit 7 months ago
Hdlab Fpga Development Board ⭐ 43
Open source FPGA development platform
most recent commit 9 months ago
My Verilog Examples ⭐ 22
A place to keep my synthesizable verilog examples.
most recent commit a year ago
Svlogger ⭐ 11
SystemVerilog Logger
most recent commit a year ago
Mastering Fpgasic Book ⭐ 8
📖 Mastering FPGASIC Book
most recent commit 2 years ago
Spinalhdl Template ⭐ 8
Mill template for beginning your SpinalHDL project
most recent commit a year ago
Wrapped_rgb_mixer ⭐ 7
Demo project for the Zero to ASIC Course.
most recent commit a year ago
Apogeorv ⭐ 6
A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.
most recent commit 4 months ago
Libsv ⭐ 6
An open source, parameterized SystemVerilog digital hardware IP library
total releases 3most recent commit 2 years ago
Frequency_counter ⭐ 6
Project 2.2 Frequency counter
most recent commit a year ago
Gost 28147 89 ⭐ 5
Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher
most recent commit 7 years ago
Tinyuart ⭐ 5
Lightweight UART core in VHDL
most recent commit 2 years ago
The 2 Most Depended On Asic Hdl Open Source Projects
Dfiant ⭐ 56
DFiant: A Dataflow Hardware Descripition Language
dependent packages 4total releases 3latest release September 05, 2023most recent commit 7 months ago
Pygears ⭐ 93
HW Design: A Functional Approach
dependent packages 1total releases 21latest release October 28, 2018most recent commit 2 years agopypi pygears} Downloads
The 4 Latest Releases In Asic Hdl Open Source Projects
Dfiant ⭐ 56
DFiant: A Dataflow Hardware Descripition Language
dependent packages 4total releases 3latest release September 05, 2023most recent commit 7 months ago
Libsv ⭐ 6
An open source, parameterized SystemVerilog digital hardware IP library
total releases 3latest release January 31, 2022most recent commit 2 years ago
Pygears ⭐ 93
HW Design: A Functional Approach
dependent packages 1total releases 21latest release October 28, 2018most recent commit 2 years agopypi pygears} Downloads
Livehd ⭐ 192
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
total releases 4latest release June 06, 2018most recent commit 3 months ago
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