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The Top 14 Fpga Rtl Asic Open Source Projects

Open source projects categorized as Fpga Rtl Asic
Categories > Hardware > Asic
Categories > Hardware > Fpga
Axi ⭐ 834
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
most recent commit 4 months ago
Cores ⭐ 302
Various HDL (Verilog) IP Cores
most recent commit 3 years ago
Esp ⭐ 267
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
most recent commit 4 months ago
Rggen ⭐ 261
Code generation tool for configuration and status registers
total releases 62most recent commit 3 months ago
Surf ⭐ 259
A huge VHDL library for FPGA development
most recent commit 5 months ago
Open Register Design Tool ⭐ 169
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
most recent commit 9 months ago
Tekno Kizil ⭐ 129
KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi
most recent commit 9 months ago
Logic ⭐ 121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
most recent commit 4 years ago
Vga Clock ⭐ 33
Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
most recent commit 2 years ago
Design And Asic Implementation Of 32 Point Fft Processor ⭐ 20
I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of a
most recent commit 5 months ago
Gatery ⭐ 14
Gatery, a library for circuit design.
most recent commit 8 months ago
Hdl Modules ⭐ 10
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
most recent commit 3 months ago
Peakrdl Verilog ⭐ 8
Generate verilog register file from systemRDL description
most recent commit a year ago
Gost 28147 89 ⭐ 5
Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher
most recent commit 7 years ago
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