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The Top 17 Python Fpga Asic Open Source Projects

Open source projects categorized as Python Fpga Asic
Fusesoc ⭐ 1,065
Package manager and build abstraction tool for FPGA/ASIC development
dependent packages 5total releases 26most recent commit 3 months agopypi fusesoc} Downloads
Poc ⭐ 324
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
most recent commit 4 years ago
Surf ⭐ 259
A huge VHDL library for FPGA development
most recent commit 5 months ago
Systemrdl Compiler ⭐ 212
SystemRDL 2.0 language compiler front-end
dependent packages 14total releases 50most recent commit 3 months agopypi systemrdl-compiler} Downloads
Mflowgen ⭐ 169
mflowgen -- A Modular ASIC/FPGA Flow Generator
total releases 6most recent commit 3 months ago
Pygears ⭐ 93
HW Design: A Functional Approach
dependent packages 1total releases 21most recent commit 2 years agopypi pygears} Downloads
Corsair ⭐ 52
Control and Status Register map generator for HDL projects
total releases 8most recent commit a year ago
Peakrdl ⭐ 48
Control and status register code generator toolchain
dependent packages 4total releases 11most recent commit 5 months agopypi peakrdl} Downloads
Peakrdl Uvm ⭐ 41
Generate UVM register model from compiled SystemRDL input
total releases 10most recent commit 5 months ago
Awesome Hwd Tools ⭐ 41
A curated list of awesome open source hardware design tools
most recent commit a year ago
Peakrdl Regblock ⭐ 36
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
total releases 20most recent commit 3 months ago
Peakrdl Ipxact ⭐ 29
Import and export IP-XACT XML register models
dependent packages 2total releases 17most recent commit 5 months agopypi peakrdl-ipxact} Downloads
Deepsocflow ⭐ 28
An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
most recent commit 4 months ago
Mera ⭐ 22
A Heterogeneous Platform Deep Learning Compiler Framework from EdgeCortix
most recent commit 4 months ago
Aes Gcm 128 192 256 Bits ⭐ 14
Configurable AES-GCM IP (128, 192, 256 bits)
most recent commit 4 months ago
Regenerate ⭐ 7
Manages registers for ASIC and FPGA designs
most recent commit 4 years ago
Fold ⭐ 7
high abstraction synthesis
most recent commit 3 months ago
The 5 Most Depended On Python Fpga Asic Open Source Projects
Systemrdl Compiler ⭐ 212
SystemRDL 2.0 language compiler front-end
dependent packages 14total releases 50latest release November 09, 2023most recent commit 3 months agopypi systemrdl-compiler} Downloads
Fusesoc ⭐ 1,065
Package manager and build abstraction tool for FPGA/ASIC development
dependent packages 5total releases 26latest release November 17, 2023most recent commit 3 months agopypi fusesoc} Downloads
Peakrdl ⭐ 48
Control and status register code generator toolchain
dependent packages 4total releases 11latest release October 26, 2023most recent commit 5 months agopypi peakrdl} Downloads
Peakrdl Ipxact ⭐ 29
Import and export IP-XACT XML register models
dependent packages 2total releases 17latest release August 31, 2023most recent commit 5 months agopypi peakrdl-ipxact} Downloads
Pygears ⭐ 93
HW Design: A Functional Approach
dependent packages 1total releases 21latest release October 28, 2018most recent commit 2 years agopypi pygears} Downloads
The 9 Latest Releases In Python Fpga Asic Open Source Projects
Fusesoc ⭐ 1,065
Package manager and build abstraction tool for FPGA/ASIC development
dependent packages 5total releases 26latest release November 17, 2023most recent commit 3 months agopypi fusesoc} Downloads
Systemrdl Compiler ⭐ 212
SystemRDL 2.0 language compiler front-end
dependent packages 14total releases 50latest release November 09, 2023most recent commit 3 months agopypi systemrdl-compiler} Downloads
Peakrdl ⭐ 48
Control and status register code generator toolchain
dependent packages 4total releases 11latest release October 26, 2023most recent commit 5 months agopypi peakrdl} Downloads
Peakrdl Regblock ⭐ 36
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
total releases 20latest release October 12, 2023most recent commit 3 months ago
Mflowgen ⭐ 169
mflowgen -- A Modular ASIC/FPGA Flow Generator
total releases 6latest release September 21, 2023most recent commit 3 months ago
Peakrdl Ipxact ⭐ 29
Import and export IP-XACT XML register models
dependent packages 2total releases 17latest release August 31, 2023most recent commit 5 months agopypi peakrdl-ipxact} Downloads
Peakrdl Uvm ⭐ 41
Generate UVM register model from compiled SystemRDL input
total releases 10latest release July 29, 2022most recent commit 5 months ago
Corsair ⭐ 52
Control and Status Register map generator for HDL projects
total releases 8latest release September 26, 2021most recent commit a year ago
Pygears ⭐ 93
HW Design: A Functional Approach
dependent packages 1total releases 21latest release October 28, 2018most recent commit 2 years agopypi pygears} Downloads
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