Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
---|---|---|---|---|---|---|---|---|---|---|
Pipelinec | 519 | 3 months ago | 82 | gpl-3.0 | Python | |||||
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature. | ||||||||||
Opl3_fpga | 225 | 4 years ago | 6 | lgpl-3.0 | VHDL | |||||
Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer | ||||||||||
Vhdl Extras | 156 | a year ago | 3 | VHDL | ||||||
Flexible VHDL library | ||||||||||
Symbolator | 73 | 2 | 4 years ago | 3 | October 19, 2017 | 12 | mit | Python | ||
HDL symbol generator | ||||||||||
Sdram Fpga | 65 | 4 years ago | 3 | mit | VHDL | |||||
A FPGA core for a simple SDRAM controller. | ||||||||||
Q27 | 53 | 7 years ago | 1 | agpl-3.0 | VHDL | |||||
27-Queens Puzzle: Massively Parellel Enumeration and Solution Counting | ||||||||||
Siafpgaminer | 44 | 6 years ago | 1 | mit | VHDL | |||||
VHDL FPGA design of an optimized Blake2b pipeline to mine Siacoin | ||||||||||
Rudi Rv32i | 41 | 4 years ago | 2 | mit | VHDL | |||||
A rudimental RISCV CPU supporting RV32I instructions, in VHDL | ||||||||||
Appleiisd | 37 | 3 years ago | 2 | VHDL | ||||||
SD card based ProFile replacement for IIe | ||||||||||
Vhdl Hdmi Out | 33 | 2 years ago | 1 | mit | VHDL | |||||
HDMI Out VHDL code for 7-series Xilinx FPGAs |