Swerv_eh1_fpga
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Vexriscv | 2,135 | 4 months ago | 100 | mit | Assembly | |||||
| A FPGA friendly 32 bit RISC-V CPU implementation | ||||||||||
| Cva6 | 2,042 | 22 days ago | 157 | other | Assembly | |||||
| The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux | ||||||||||
| Darkriscv | 1,795 | 5 months ago | 9 | bsd-3-clause | Verilog | |||||
| opensouce RISC-V cpu core implemented in Verilog from scratch in one night! | ||||||||||
| E200_opensource | 1,688 | 3 years ago | 33 | apache-2.0 | Verilog | |||||
| Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2 | ||||||||||
| Neorv32 | 1,337 | 3 months ago | 15 | bsd-3-clause | VHDL | |||||
| 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. | ||||||||||
| Serv | 1,158 | 4 months ago | 17 | isc | Verilog | |||||
| SERV - The SErial RISC-V CPU | ||||||||||
| Tinyriscv | 865 | 5 months ago | 8 | apache-2.0 | C | |||||
| A very simple and easy to understand RISC-V core. | ||||||||||
| Riscv Cores List | 778 | 3 years ago | n,ull | |||||||
| RISC-V Cores, SoC platforms and SoCs | ||||||||||
| Firesim | 778 | 3 months ago | 218 | other | Scala | |||||
| FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility | ||||||||||
| Cores Veer Eh1 | 770 | a year ago | 14 | apache-2.0 | SystemVerilog | |||||
| VeeR EH1 core | ||||||||||
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