Sieav
Co-simulation and behavioural verification with VHDL, C/C++ and Python/m
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Fp23fftk | 31 | 2 years ago | gpl-3.0 | VHDL | ||||||
| Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL). | ||||||||||
| Math | 15 | 4 years ago | n,ull | gpl-3.0 | MATLAB | |||||
| Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.) | ||||||||||
| Sieav | 10 | a year ago | VHDL | |||||||
| Co-simulation and behavioural verification with VHDL, C/C++ and Python/m | ||||||||||
| Synthowheel | 8 | 5 years ago | other | VHDL | ||||||
| Polyphonic additive wheeltone synthesizer core | ||||||||||
| Blackman_harris_win | 5 | 4 years ago | n,ull | gpl-3.0 | VHDL | |||||
| Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CORDIC like as DDS (sine / cosine generator) | ||||||||||
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