|Project Name||Stars||Downloads||Repos Using This||Packages Using This||Most Recent Commit||Total Releases||Latest Release||Open Issues||License||Language|
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|Adl3||46||8 years ago||4||April 18, 2012||mit||Python|
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|Rc4||2||2 years ago||Verilog|
|An experimental RC4 hardware implementation with one cycle/iteration performance.|
|Time a snippet.|
|Perfmetrics||1||6 years ago||mit||C++|
|Performance Metrics for code optimization|
|Btech_final_year_project||1||3 years ago||TeX|
This is an experimental hardware implementation of the RC4 stream cipher.
The core implements the cipher using memories with many read and write ports in order to be able to generate a keystream byte every cycle. The question is if the achieved clock frequency is to low to make the core usable. The answer after implementation the design in a FPGA device is that, yes it does work. The reusulting implementation achieves a clock frequency high enough to be usable. The design however is rather large.
Also, RC4 is a very, very broken cipher. Nobody should be using RC4. So don't use this core, ok?
The core implements RC4 including the arcfour128 and arcfour256 versions specified in RFC4 4345. This means support for skipping the first 1536 keystream bytes. Currently the only key sizes supported are 128 and 256 bits.
The synthesis and mapping tool you use might not be able to map the key and state memories to memory blocks available in the target technology, but instead end up using separate registers. The reason for this is a combination of many ports and asynchronous reads. The many ports can be handled by memory mirroring, but the asynchronous read ports are needed to achieve the one cycle/byte performance.
This core is supported by the FuseSoC core package manager and build system. Some quick FuseSoC instructions:
pip install fusesoc
Create and enter a new workspace
mkdir workspace && cd workspace
Register rc4 as a library in the workspace
fusesoc library add rc4 /path/to/rc4
...if repo is available locally or... ...to get the upstream repo
fusesoc library add rc4 https://github.com/secworks/rc4
To run lint
fusesoc run --target=lint secworks:crypto:rc4
Run tb_rc testbench
fusesoc run --target=tb_rc4 secworks:crypto:rc4
Run with modelsim instead of default tool (icarus)
fusesoc run --target=tb_rc4 --tool=modelsim secworks:crypto:rc4
List all targets
fusesoc core show secworks:crypto:rc4
Altera Cyclone IV GX
(2014-01-23): First complete implementation. Still not debugged.
(2014-01-17) Most parts of the functionality is done. The key size has been limited to 128 and 256 bits for the first version. The RTL is still not complete and no testbench is available.
(2014-01-13) Repo init.