Starred Repos
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Ustc Rvsoc | 261 | 7 months ago | 4 | gpl-3.0 | SystemVerilog | |||||
| An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。 | ||||||||||
| Starred Repos | 14 | 2 years ago | ||||||||
| List of repos I starred. | ||||||||||
| Machine Emulator Rom | 9 | 8 months ago | 2 | apache-2.0 | C++ | |||||
| Cartesi Machine Emulator ROM | ||||||||||
| Fpga_riscv_cpu | 6 | a year ago | mit | Verilog | ||||||
| fpga verilog risc-v rv32i cpu | ||||||||||
| Img_rom | 6 | a year ago | lgpl-3.0 | Python | ||||||
| Various scripts to create a VHDL or verilog ROM file from an image in PPM PGM or PBM format, also from a NES ROM, or a RISC-V dump memory file | ||||||||||
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