KicadJE_SympleSequencer

Designed to fit the faceplate of a Hexinverter SympleSeq E2 faceplate from Re:Synthesis

Purpose

1 - Match Hexinverter sch with Resynthesis panel

Rev 2

Status - Mouted - testing

Initial

Stage	Detail	Status
create material	sch/pcb	OK
	gerber	OK
production		ok
	produced	ok
	delivered	ok

Preliminary validation

Test	Detail	Status
Initial Inspection	clock board	ok
Initial Inspection	control board	ok
Initial Technical Test		100n capacitors in series w output is replaced w 2k
Initial Product Test		100n C101 capacitor parallel w 150k
Initial Product Test		ongoing

Secondary validation

Test	Detail	Status
Product Test	CV
Product Test	Gate
Product Test	Clock internal
Product Test	Clock in
Product Test	Clock out
Product Test	Reset In/Button
Product Test	Hold In/Button
Quality	CV
Quality	Gate
Long Term Product Test		Good
Power Draw

Errata

Errata - clock

Series capacitors not working with reset (overloads CD4017)

replace w resistors (2k and 9k1 tested and working fine)

Hold not working

Either swap R206 100k pullup with 22k-47k and R212 10k with 100k or tie hold to +12v works

Errata - control

Issues and Notes

Clock

1 - diodes for hold input
2 - diodes for reset input
3 - Gate AND Clock for gate output to reset between gates - consider making a phase adjust for shorter/longer gates
4 - OPEN resistor from Internal CLK to 4017 clock in (for use with Sequencer A that does not take slave clk input)

Control

1 - switches still reversed
2 - diode missing for reset
3 - consider moving resistors from clk module to control as there is plenty of room

Schematics

Pictures

Rev 1

Status - Installed in rack - tweaking

Initial

Stage	Detail	Status
create material	sch/pcb	OK
	gerber	OK
production		ok
	produced	ok
	delivered	ok

Preliminary validation

Test	Detail	Status
Initial Inspection	clock board	ok - the jacks are 0,5-1mm too far away from the edge
Initial Inspection	control board	ok - see errata 3
Initial Technical Test		ok
Initial Product Test		ok

Secondary validation

Test	Detail	Status
Product Test	CV	ok
Product Test	Gate	See errata 4
Product Test	Clock internal	ok - a bit slow
Product Test	Clock in	ok
Product Test	Clock out	ok - could need a buffer
Product Test	Reset In/Button	ok
Product Test	Hold In/Button	ok - needs debounce
Quality	CV	Good
Quality	Gate	No good - needs shorter pulses
Long Term Product Test		Good
Power Draw

Project Name	Stars	Most Recent Commit	Open Issues	License	Language
Pipelinec	480	5 days ago	81	gpl-3.0	Python
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Async_fifo	133	6 months ago		other	Verilog
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Blip Buf	5	3 years ago		lgpl-2.1	C++
Automatically exported from code.google.com/p/blip-buf
Timing Driven Variation Aware Clock Mesh Synthesis	4	8 years ago		other	Verilog
Timing-Driven Variation-Aware Clock Mesh Synthesis Environment; programmed in Perl and TCL scripts
Ad9851	2	4 years ago			C++
Arduino library to control the AD9851 Direct Digital Synthesis (DDS) chip or module.
Khu_sensor_65n	1	3 years ago			Verilog
khu_sensor_65n
Clock Tree Synthesis Gui	1	6 years ago			Python
A Graphical User Interface for data visualization for clock tree synthesis
Vga_project	1	a year ago			VHDL

Zynq_hls_ddr_axi_ips_multiple_clock	1	4 years ago			VHDL

Kicadje_symplesequencer	1	2 years ago			HTML
Designed to fit the faceplate of a Hexinverter SympleSeq E2 faceplate from Re:Synthesis

Kicadje_symplesequencer

KicadJE_SympleSequencer

Purpose

Rev 2

Status - Mouted - testing

Initial

Preliminary validation

Secondary validation