Riscv Coq
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Bedrock2 | 266 | 3 months ago | 51 | mit | Coq | |||||
| A work-in-progress language and compiler for verified low-level programming | ||||||||||
| Riscv Coq | 92 | 5 months ago | 5 | bsd-3-clause | Coq | |||||
| RISC-V Specification in Coq | ||||||||||
| Riscvspecformal | 58 | 4 years ago | apache-2.0 | Haskell | ||||||
| The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools. | ||||||||||
| Ace Riscv | 14 | 3 months ago | apache-2.0 | Rust | ||||||
| Assured Confidential Execution (ACE) for RISC-V | ||||||||||
| Friscv | 12 | 4 months ago | 1 | mit | Coq | |||||
| RISCV CPU implementation in SystemVerilog | ||||||||||
| Riscv Coq | 10 | 6 years ago | 1 | bsd-3-clause | Coq | |||||
| RISC-V Specification in Coq | ||||||||||
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