Avsdpll_1v8
8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Avsdpll_1v8 | 65 | 3 years ago | gpl-2.0 | |||||||
| 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature. | ||||||||||
| Siafpgaminer | 44 | 6 years ago | 1 | mit | VHDL | |||||
| VHDL FPGA design of an optimized Blake2b pipeline to mine Siacoin | ||||||||||
| Vga Clock | 33 | 2 years ago | 1 | apache-2.0 | Verilog | |||||
| Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle. | ||||||||||
Alternatives To Avsdpll_1v8Select To Compare
Alternative Project Comparisons
Popular Clock Projects
Popular Asic Projects
Popular User Interface Components Categories
Related Searches
Get A Weekly Email With Trending Projects For These Categories
No Spam. Unsubscribe easily at any time.
Clock
Asic