Project Name	Stars	Repos Using This	Packages Using This	Most Recent Commit	Total Releases	Latest Release	Open Issues	License	Language
Chisel	3,962		9	2 months ago	59	April 14, 2023	397	apache-2.0	Scala
Chisel: A Modern Hardware Design Language
Iverilog	2,521			a year ago			125	gpl-2.0	C++
Icarus Verilog
Vexriscv	2,135			a year ago			100	mit	Assembly
A FPGA friendly 32 bit RISC-V CPU implementation
Verilator	1,934		1	10 months ago	8	October 04, 2022	304	lgpl-3.0	C++
Verilator open-source SystemVerilog simulator and lint system
Nyuziprocessor	1,863			a year ago			90	apache-2.0	C
GPGPU microprocessor architecture
Cocotb	1,828	9	22	7 days ago	44	October 06, 2023	415	bsd-3-clause	Python
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Darkriscv	1,795			a year ago			9	bsd-3-clause	Verilog
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Verilog Ethernet	1,768			a year ago			98	mit	Verilog
Verilog Ethernet components for FPGA implementation
E200_opensource	1,688			4 years ago			33	apache-2.0	Verilog
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
Fromthetransistor	1,607			3 years ago			16
From the Transistor to the Web Browser, a rough outline for a 12 week course

Alternatives To Hardcaml_verilator

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Chisel ⭐ 3,962

Chisel: A Modern Hardware Design Language

dependent packages 9total releases 59most recent commit 2 months ago

Iverilog ⭐ 2,521

Icarus Verilog

most recent commit a year ago

Vexriscv ⭐ 2,135

A FPGA friendly 32 bit RISC-V CPU implementation

most recent commit a year ago

Verilator ⭐ 1,934

Verilator open-source SystemVerilog simulator and lint system

dependent packages 1total releases 8most recent commit 10 months ago

Nyuziprocessor ⭐ 1,863

GPGPU microprocessor architecture

most recent commit a year ago

Cocotb ⭐ 1,828

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

dependent packages 22total releases 44most recent commit 7 days ago

Darkriscv ⭐ 1,795

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

most recent commit a year ago

Verilog Ethernet ⭐ 1,768

Verilog Ethernet components for FPGA implementation

most recent commit a year ago

E200_opensource ⭐ 1,688

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

most recent commit 4 years ago

Fromthetransistor ⭐ 1,607

From the Transistor to the Web Browser, a rough outline for a 12 week course

most recent commit 3 years ago

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Hardcaml_verilator vs Chisel

Hardcaml_verilator vs Iverilog

Hardcaml_verilator vs Vexriscv

Hardcaml_verilator vs Verilator

Hardcaml_verilator vs Nyuziprocessor

Hardcaml_verilator vs Cocotb

Hardcaml_verilator vs Darkriscv

Hardcaml_verilator vs Verilog Ethernet

Hardcaml_verilator vs E200_opensource

Hardcaml_verilator vs Fromthetransistor

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