Cryptocurrencies
LabVIEW FPGA Framework for Implementing Cryptomining Algorithms
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Silice | 1,199 | 3 months ago | 73 | other | C++ | |||||
| Silice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures. | ||||||||||
| Hdlab Fpga Development Board | 43 | 9 months ago | mit | VHDL | ||||||
| Open source FPGA development platform | ||||||||||
| Clash Utils | 42 | 10 months ago | 8 | bsd-3-clause | Haskell | |||||
| A collection of reusable Clash designs/examples | ||||||||||
| Grassrootsstartup Computervsion Zynq | 35 | a year ago | other | C | ||||||
| Sift Implementation In Verilog | 21 | 10 years ago | ||||||||
| Using Verilog to implement the SIFT algorithm into an FPGA for small robotic situations | ||||||||||
| Myhdl Based Fpga Dsp Toolflow | 21 | 12 years ago | Python | |||||||
| A library for generating Software Defined Radio-intended DSP code for FPGAs that makes use of the MyHDL (www.myhdl.org) Python library. Targeted at the Rhino Project (see URL). | ||||||||||
| Booth_multipliers | 19 | 4 years ago | Verilog | |||||||
| Parameterized Booth Multiplier in Verilog 2001 | ||||||||||
| Fpga Cryptoparty | 18 | 7 years ago | 3 | gpl-3.0 | Java | |||||
| A very very fast VHDL implementation of the WPA2 encryption algorithm. | ||||||||||
| Pipecnn_winograd | 17 | 3 years ago | 5 | other | C++ | |||||
| An OpenCL-Based FPGA Accelerator for Compressed YOLOv2 | ||||||||||
| Xilinx_fpga_hls Mapping Neural Network To Hardware | 14 | 5 years ago | 2 | mit | ||||||
| At present, just an example to show how to map the detection algorithm YOLOv2 from model to FPGA | ||||||||||
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