Clock Tree Synthesis Gui
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Pipelinec | 480 | 2 days ago | 81 | gpl-3.0 | Python | |||||
| A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature. | ||||||||||
| Async_fifo | 133 | 6 months ago | other | Verilog | ||||||
| A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog | ||||||||||
| Blip Buf | 5 | 3 years ago | lgpl-2.1 | C++ | ||||||
| Automatically exported from code.google.com/p/blip-buf | ||||||||||
| Timing Driven Variation Aware Clock Mesh Synthesis | 4 | 8 years ago | other | Verilog | ||||||
| Timing-Driven Variation-Aware Clock Mesh Synthesis Environment; programmed in Perl and TCL scripts | ||||||||||
| Ad9851 | 2 | 4 years ago | C++ | |||||||
| Arduino library to control the AD9851 Direct Digital Synthesis (DDS) chip or module. | ||||||||||
| Khu_sensor_65n | 1 | 3 years ago | Verilog | |||||||
| khu_sensor_65n | ||||||||||
| Clock Tree Synthesis Gui | 1 | 6 years ago | Python | |||||||
| A Graphical User Interface for data visualization for clock tree synthesis | ||||||||||
| Vga_project | 1 | a year ago | VHDL | |||||||
| Zynq_hls_ddr_axi_ips_multiple_clock | 1 | 4 years ago | VHDL | |||||||
| Kicadje_symplesequencer | 1 | 2 years ago | HTML | |||||||
| Designed to fit the faceplate of a Hexinverter SympleSeq E2 faceplate from Re:Synthesis | ||||||||||
Clock-Tree-Synthesis-GUI
A Graphical User Interface for data visualization for clock tree synthesis Authors: Jacob Baron and Scott Lerner
How to Use: In order to use this program, you'll need a .im file formatted correctly. For now, in order to chose the file, you'll need to rename the "filename" variable. This variable can be found immediately after the Linked List Class declaration.
In addition to changing the variable name, you'll also need to change one more item-- the "padding" variable (This will not be necessary in a future release of this software). The padding variable is used to help the program determine how many nodes lack certain attributes (ie, left child, right child, original permissible region, permissible region, and distance).
Refer to the comments within the code if you have any issues.
Features: Graphical User Interface for plotting of .im files for clock tree synthesis, Search feature for finding nodes more easily, Display feature to print relevent information of the nodes into a window and circle the node in the plot, Clear feature that removes the detailed node information and any circled nodes in the plot, Zoom feature now available for plot
Future Work: Add return support for the search bar
