F4pga V2x
Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Ipxact2systemverilog | 55 | 5 months ago | 24 | November 26, 2023 | 2 | gpl-2.0 | Python | |||
| Translates IPXACT XML to synthesizable VHDL or SystemVerilog | ||||||||||
| Verilog Utils | 32 | 9 years ago | Verilog | |||||||
| native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches | ||||||||||
| Sdaccel_chisel_integration | 16 | 6 years ago | apache-2.0 | Verilog | ||||||
| Chisel Project for Integrating RTL code into SDAccel | ||||||||||
| Hdlgen Chatgpt | 9 | 3 months ago | 14 | agpl-3.0 | Python | |||||
| HDLGen-ChatGPT, works in tandem with ChatGPT-3.5 chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project | ||||||||||
| F4pga V2x | 8 | 2 years ago | 44 | apache-2.0 | Python | |||||
| Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow. | ||||||||||
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