Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
---|---|---|---|---|---|---|---|---|---|---|
Litex | 2,546 | 2 months ago | 239 | other | C | |||||
Build your hardware, easily! | ||||||||||
Vexriscv | 2,135 | 3 months ago | 100 | mit | Assembly | |||||
A FPGA friendly 32 bit RISC-V CPU implementation | ||||||||||
Cva6 | 2,029 | 6 days ago | 157 | other | Assembly | |||||
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux | ||||||||||
Darkriscv | 1,795 | 4 months ago | 9 | bsd-3-clause | Verilog | |||||
opensouce RISC-V cpu core implemented in Verilog from scratch in one night! | ||||||||||
E200_opensource | 1,688 | 3 years ago | 33 | apache-2.0 | Verilog | |||||
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2 | ||||||||||
Neorv32 | 1,337 | 2 months ago | 15 | bsd-3-clause | VHDL | |||||
🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. | ||||||||||
Zipcpu | 1,139 | 2 months ago | 4 | Verilog | ||||||
A small, light weight, RISC CPU soft core | ||||||||||
Tornadovm | 1,054 | 2 months ago | 21 | apache-2.0 | Java | |||||
TornadoVM: A practical and efficient heterogeneous programming framework for managed languages | ||||||||||
Oneapi Samples | 758 | 2 months ago | 61 | mit | C++ | |||||
Samples for Intel® oneAPI Toolkits | ||||||||||
E203_hbirdv2 | 741 | a year ago | 10 | apache-2.0 | Verilog | |||||
The Ultra-Low Power RISC-V Core |