Simple Analog Clock vs Timing Driven Variation Aware Clock Mesh Synthesis
| Simple Analog Clock | Timing Driven Variation Aware Clock Mesh Synthesis | |
|---|---|---|
| Stars | 20 | 4 |
| Downloads | ||
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| Most Recent Commit | 4 years ago | 7 years ago |
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| License | apache-2.0 | other |
| Programming Language | Java | Verilog |